Here, how I would think about your issue:
I assume to use a RP2350 (new one) with 150 MHz internal core clock frequency.
A) so, if I would use a PIO to sample this GPIO, I would need two instructions to do so. Even PIO runs at 150 MHz (internal core) clock: it would be able to sample just up to 75 MHz (really max. possible).
B) but even this is not really guaranteed:
There can be internal clock synchronizers, e.g. on the GPIO itself, on the AHB/APB bus fabric. A clock synchronizer is used to synchronize two different blocks (e.g. MCU core and other is peripheral, like GPIO) running with different (and independent) clocks.
A clock synchronizer needs one additional clock, or: it delays all by another 1/2 clock speed.
You have to consider how the data flows through your system: is it going directly or via bus fabrics?
What I have seen:
I would assume: if you run 150 MHz SYSCLK, just 75 MHz max. possible at all. But if anywhere a clock synchronizer is involved, e.g. also on reading or sampling GPIOs: assume another clock division by 1/2.
So, 150 MHz and divide by 4 = 37.5 MHz (as the max. "guaranteed" speed).
BTW:
even MCU is running with 150 MHz, it would never be able to read a GPIO with 50 MHz: in a loop and using the fastest assembly instruction, you might need 4 clock cycles just to execute the code. So, it goes down to 37.5 MHz.
Even, when a GPIO generates an INT: 1/2 SYSCLK to operate, with a clock synchronizer to sync the INT event on bus to MCU core - 1/4 of SYSCLK as max. speed.
My rule of thumb:
Having a core clock (SYSCLK) as 150 MHz: nothing can be "guaranteed" faster as 1/4 = 37.5 MHz, except you have real device (e.g. SPI) running with SYSCLK and needing a ratio of 1/2 = 75 MHz, without clock synchronizers involved).
Check also how your SYSCLK is set. Maybe the system is not running at "full possible speed".
I assume to use a RP2350 (new one) with 150 MHz internal core clock frequency.
A) so, if I would use a PIO to sample this GPIO, I would need two instructions to do so. Even PIO runs at 150 MHz (internal core) clock: it would be able to sample just up to 75 MHz (really max. possible).
B) but even this is not really guaranteed:
There can be internal clock synchronizers, e.g. on the GPIO itself, on the AHB/APB bus fabric. A clock synchronizer is used to synchronize two different blocks (e.g. MCU core and other is peripheral, like GPIO) running with different (and independent) clocks.
A clock synchronizer needs one additional clock, or: it delays all by another 1/2 clock speed.
You have to consider how the data flows through your system: is it going directly or via bus fabrics?
What I have seen:
- On a RP2350 (the new one), with 150 MHz core clock - the max. speed on any peripheral (like SPI, as read device) cannot get faster as 75 MHz
I would assume: if you run 150 MHz SYSCLK, just 75 MHz max. possible at all. But if anywhere a clock synchronizer is involved, e.g. also on reading or sampling GPIOs: assume another clock division by 1/2.
So, 150 MHz and divide by 4 = 37.5 MHz (as the max. "guaranteed" speed).
BTW:
even MCU is running with 150 MHz, it would never be able to read a GPIO with 50 MHz: in a loop and using the fastest assembly instruction, you might need 4 clock cycles just to execute the code. So, it goes down to 37.5 MHz.
Even, when a GPIO generates an INT: 1/2 SYSCLK to operate, with a clock synchronizer to sync the INT event on bus to MCU core - 1/4 of SYSCLK as max. speed.
My rule of thumb:
Having a core clock (SYSCLK) as 150 MHz: nothing can be "guaranteed" faster as 1/4 = 37.5 MHz, except you have real device (e.g. SPI) running with SYSCLK and needing a ratio of 1/2 = 75 MHz, without clock synchronizers involved).
Check also how your SYSCLK is set. Maybe the system is not running at "full possible speed".
Statistics: Posted by tjaekel — Sun Sep 01, 2024 10:40 pm
