This is an interesting question. To the best of my knowledge the DMA does not accumulate to create sequential frames. (RP2040 is fairly well planned. Cortex in general is a well planned ecosystem, which the RP2040 deviates from slightly.)Hmm, DMA_SIZE_8 using 8 bit SPI seems to be as fast as DMA_SIZE_16 using 16 bit SPI, but still if there is an answer, it would be nice to know.
The advantage however would be better transfer cycle utilization. However the max gain is relatively small and not likely to be used.
- PIO in theory could exploit it with user logic.
- The other devices are relatively low bandwidth.
- USB is packet by nature and supports the memory optimizations to go at max speed.
- DMA would experience priority inversion if it did not cap the accumulation to 32-bit transfers.
- This would be more complex and force a requirement on the target side.
There is a fix number of transactions which can take place. You must schedule them somewhat carefully. The DMA engine is pipelined which allows it to work fairly quick. However memory bottlenecks may create congestion which forces stalls into the pipeline. The exact internals of this have come up, but I do not believe them to be complete.
I have some recommendations for scheduling in different situations, but I am guessing those are not of interest at this time.
Statistics: Posted by dthacher — Mon Jun 03, 2024 5:50 am
