HI,
I've been banging my head against this particular wall for nearly two days now and I'm going a bit crazy.
It seems like a trivially obvious thing to do but I can't find any examples or explanation.
I want a thread on core0 to be able to trigger code on core1, on an interrupt basis, not polling.
I wasted a lot of time trying tricks like usr_irq until I noticed that one core cannot set a pending IRQ on the other core even if the ISR is set up on the other core.
Now before I need to something clunky like write to one GPIO pin with one core , wire it up to its neighbour and use that pin as an input to trigger off, can someone point to some documentation of the feature I am sure unable to find but is sitting right in front of me?
I do not need to pass any data, it's just getting one process to trigger a function on the other core to spread the load and make use of the second core.
This seems like the whole reason to have a second core so I can't see why it is so hard to find.
TIA.
I've been banging my head against this particular wall for nearly two days now and I'm going a bit crazy.
It seems like a trivially obvious thing to do but I can't find any examples or explanation.
I want a thread on core0 to be able to trigger code on core1, on an interrupt basis, not polling.
I wasted a lot of time trying tricks like usr_irq until I noticed that one core cannot set a pending IRQ on the other core even if the ISR is set up on the other core.
Now before I need to something clunky like write to one GPIO pin with one core , wire it up to its neighbour and use that pin as an input to trigger off, can someone point to some documentation of the feature I am sure unable to find but is sitting right in front of me?
I do not need to pass any data, it's just getting one process to trigger a function on the other core to spread the load and make use of the second core.
This seems like the whole reason to have a second core so I can't see why it is so hard to find.
TIA.
Statistics: Posted by pie_face — Thu Aug 08, 2024 7:01 pm