The WFI instruction is there to hint the CPU that it can sleep once all interrupts are handled, as signaled by the spurious 1023 IRQ, and until a new interrupt is raised. Just make sure to not use it with interrupt exceptions masked.
The ARM timer has to be initialized every tick, it doesn't repeat. What my code does is look up the timer frequency in Hz, set up the timer to that value whenever its interrupt handler is triggered, and re-arm the timer. The frequency is from CPRMAN and is set in CNTFRQ_EL0 by the ARM stub that is part of the firmware. The new timer value is set by writing the number of clock cycles to wait to CNTP_TVAL_EL0 (which implicitly adds the written value to CNTP_CVAL_EL0), and is armed by writing to CNTP_CTL_EL0. I chose that timer for convenience as that's the easiest timer to set up.
Also, while you didn't ask about this, I feel compelled to inform you about another potential pitfall which is that you have to add 32 to the SPIs in the device tree to get the absolute IRQ, because SPIs (Shared Peripheral Interrupts) start at IRQ 32 (IRQs 0 .. 15 are Software Generated Interrupts and IRQs 16 .. 31 are Private Peripheral Interrupts). This means that when the device tree says that a device uses SPI 48, the actual IRQ is 80.
The ARM timer has to be initialized every tick, it doesn't repeat. What my code does is look up the timer frequency in Hz, set up the timer to that value whenever its interrupt handler is triggered, and re-arm the timer. The frequency is from CPRMAN and is set in CNTFRQ_EL0 by the ARM stub that is part of the firmware. The new timer value is set by writing the number of clock cycles to wait to CNTP_TVAL_EL0 (which implicitly adds the written value to CNTP_CVAL_EL0), and is armed by writing to CNTP_CTL_EL0. I chose that timer for convenience as that's the easiest timer to set up.
Also, while you didn't ask about this, I feel compelled to inform you about another potential pitfall which is that you have to add 32 to the SPIs in the device tree to get the absolute IRQ, because SPIs (Shared Peripheral Interrupts) start at IRQ 32 (IRQs 0 .. 15 are Software Generated Interrupts and IRQs 16 .. 31 are Private Peripheral Interrupts). This means that when the device tree says that a device uses SPI 48, the actual IRQ is 80.
Statistics: Posted by Fridux — Tue Jun 11, 2024 5:50 am