Assuming you are using printf to USB serial, that is a whole kaboodle there -- a USB stack with interrupts and all. Who knows what other interrupts are operating? Anything that pulls in non-SRAM code goes through the I-cache. I-cache is gonna have misses. I have read other discussions:
viewtopic.php?t=329944
So apparently I-cache is 16KB cache 2-way set associative. Pretty much impossible to depend on it not missing -- perhaps one can adapt the SDK to 100% SRAM operation, but that would take a whole lot of code reviews and audits.
Other MCUs such as PIC32s updated their ADCs to have autonomous operating modes when flash speeds started to lag and they had to insert small caches. So a reasonable solution is to use the autonomous modes of the Pico ADC if low jitter is a requirement.
viewtopic.php?t=329944
So apparently I-cache is 16KB cache 2-way set associative. Pretty much impossible to depend on it not missing -- perhaps one can adapt the SDK to 100% SRAM operation, but that would take a whole lot of code reviews and audits.
Other MCUs such as PIC32s updated their ADCs to have autonomous operating modes when flash speeds started to lag and they had to insert small caches. So a reasonable solution is to use the autonomous modes of the Pico ADC if low jitter is a requirement.
Statistics: Posted by katak255 — Fri May 03, 2024 11:32 am