Well, we already had a hardware that was running fine in Pi3 and Pi4 models with it's own CSYNC combiner. I even have a hardware prototype running without the csync circuit using a custom kernel vc4 module adding changes to output native csync from the raspberry. It worked fine in Pi4 (never tested in 3):
https://github.com/raspberrypi/linux/co ... 026d8fc631
Also interlaced worked fine, whether they were meant to be officially supported or not. I was able to generate any modeline via switchres calculator and all of them worked in Pi4 model, progressive, interlaced, normal res, super res...
Pi5 also works fine with all this stuff but the interlaced ones wich breaks compatibility.
https://github.com/raspberrypi/linux/co ... 026d8fc631
Also interlaced worked fine, whether they were meant to be officially supported or not. I was able to generate any modeline via switchres calculator and all of them worked in Pi4 model, progressive, interlaced, normal res, super res...
Pi5 also works fine with all this stuff but the interlaced ones wich breaks compatibility.
Statistics: Posted by rTomasa — Thu May 02, 2024 11:42 am